In recent years, development of thin film transistors (TFT) that can be formed over flexible plastic substrates or paper substrates has been actively pursued in order to realize sheet displays, sheet computers, and the like. Consequently, it is an important challenge to respond to a demand that a TFT be able to be manufactured at a temperature that is equal to or lower than an allowable temperature limit of a substrate.
However, manufacturing the TFT at a temperature that is equal to or lower than the allowable temperature limit of the substrate means that heating at high temperature cannot be performed, and this causes problems. For example, a problem occurs in which an on current and mobility which are TFT characteristics are degraded due to insufficient contact between a wiring and a semiconductor film.
As an example of a pixel TFT provided for a display device, there is a bottom gate TFT in which a gate electrode is positioned under a semiconductor layer and a gate insulating film. Further, among bottom gate TFTs, there is a top contact type in which a source electrode and a drain electrode are positioned over the semiconductor layer (see FIG. 2A), as well as a bottom contact type in which the source electrode and the drain electrode are positioned under the semiconductor layer (see FIG. 2B) (refer to Patent Document 1: Japanese Published Patent Application No. 2005-223048). 
A top contact type bottom gate TFT shown in FIG. 2A includes a gate electrode 1002 over a substrate 1001, a gate insulating film 1003 over the gate electrode 1002, and a semiconductor film 1004 over the gate insulating film 1003. Further, electrodes 1005 each functioning as a source electrode or drain electrode (hereinafter referred to as source or drain electrodes 1005. Note that in this specification, “source or drain electrodes” mean that each of the electrodes may function as a source electrode or a drain electrode) are formed over the semiconductor film 1004. When voltage is applied to the gate electrode 1002, a source region or a drain region is formed in each of regions of the semiconductor film 1004 that are in contact with the source or drain electrodes 1005, and a channel forming region is formed in the semiconductor film 1004 above the gate electrode 1002 and between the source region and the drain region.
A bottom contact type bottom gate TFT shown in FIG. 2B includes a gate electrode 1012 over a substrate 1011, a gate insulating film 1013 over the gate electrode 1012, and source or drain electrodes 1014 over the gate insulating film 1013. Further, the bottom contact type bottom gate TFT includes a semiconductor film 1015 over the gate insulating film 1013 and the source or drain electrodes 1014. When voltage is applied to the gate electrode 1012, a source region or a drain region is formed in each of regions of the semiconductor film 1015 that are in contact with the source or drain electrodes 1014, and a channel forming region is formed in the semiconductor film 1015 above the gate electrode 1012 and between the source region and the drain region.
In a top contact type bottom gate TFT (FIG. 2A) and in a bottom contact type bottom gate TFT (FIG. 2B) in which the source electrode and the drain electrode are positioned under the semiconductor layer, contact between the semiconductor film and electrodes or wirings is poor if a heat treatment is not sufficiently performed, and an on current and mobility are degraded. Therefore, a heat treatment at around 300° C. is usually performed. However, when a substrate is made of a material with a low allowable temperature limit instead of a material with a high allowable temperature limit,  such as plastic or paper, the heat treatment cannot be performed at such a temperature.
Further, although it is necessary that film thicknesses of electrodes or wirings are thick in order to lower wiring resistance, in the bottom contact type bottom gate TFT shown in FIG. 2B, there is concern that coverage of the semiconductor film and the source or drain electrodes becomes poor. Consequently, degradation in TFT characteristics occurs.